QuadroCopter  0.1.4
LSM303DLHC.h
Go to the documentation of this file.
1 /*
2 Copyright (C) 2017 Michael Brookes
3 
4 This program is free software: you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation, either version 3 of the License, or
7 (at your option) any later version.
8 
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13 
14 You should have received a copy of the GNU General Public License
15 along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17 
18 #ifndef SRC_LSM303DLHC_H_
19 #define SRC_LSM303DLHC_H_
20 
21 #include "../../i2cDevice.h"
22 #include <bitset>
23 
24 #define MICRO_SECOND = 1000000
25 /*
26  * REGISTER ADDRESS
27  */
28 //From Table 17. of the LSM303 Data sheet ( lib/docs/LSM303DLHC.PDF )
29 #define ACCEL_ADDRESS 0x19
30 #define CTRL_REG1_A 0x20
31 #define CTRL_REG2_A 0x21
32 #define CTRL_REG3_A 0x22
33 #define CTRL_REG4_A 0x23
34 #define CTRL_REG5_A 0x24
35 #define CTRL_REG6_A 0x25
36 #define REFERENCE_A 0x26
37 #define STATUS_REG_A 0x27
38 #define OUT_X_L_A 0x28
39 #define OUT_X_H_A 0x29
40 #define OUT_Y_L_A 0x2A
41 #define OUT_Y_H_A 0x2B
42 #define OUT_Z_L_A 0x2C
43 #define OUT_Z_H_A 0x2D
44 #define FIFO_CTRL_REG_A 0x2E
45 #define FIFO_SRC_REG_A 0x2F
46 #define INT1_CFG_A 0x30
47 #define INT1_SOURCE_A 0x31
48 #define INT1_THS_A 0x32
49 #define INT1_DURATION_A 0x33
50 #define INT2_CFG_A 0x34
51 #define INT2_SOURCE_A 0x35
52 #define INT2_THS_A 0x36
53 #define INT2_DURATION_A 0x37
54 #define CLICK_CFG_A 0x38
55 #define CLICK_SRC_A 0x39
56 #define CLICK_THS_A 0x3A
57 #define TIME_LIMIT_A 0x3B
58 #define TIME_LATENCY_A 0x3C
59 #define TIME_WINDOW_A 0x3D
60 
61 #define MAG_ADDRESS 0x1E
62 #define CRA_REG_M 0x00
63 #define CRB_REG_M 0x01
64 #define MR_REG_M 0x02
65 #define OUT_X_H_M 0x03
66 #define OUT_X_L_M 0x04
67 #define OUT_Z_H_M 0x05
68 #define OUT_Z_L_M 0x06
69 #define OUT_Y_H_M 0x07
70 #define OUT_Y_L_M 0x08
71 #define SR_REG_Mg 0x09
72 #define IRA_REG_M 0x0A
73 #define IRB_REG_M 0x0B
74 #define IRC_REG_M 0x0C
75 #define TEMP_OUT_H_M 0x31
76 #define TEMP_OUT_L_M 0x32
77 /*
78  * END OF REGISTER ADDRESSES
79  */
80 
81 /*
82  * POWER SETTINGS - REGISTER TO WRITE TO : CTRL_REG1_A 0x20
83  */
84 #define POWER_OFF 0b00000000
85 #define ODR_1HZ 0b00010000
86 #define ODR_10HZ 0b00100000
87 #define ODR_25HZ 0b00110000
88 #define ODR_50HZ 0b01000000
89 #define ODR_100HZ 0b01010000
90 #define ODR_200HZ 0b01100000
91 #define ODR_400HZ 0b01110000
92 #define ODR_1344KHZ 0b10010000
93 #define LP_LOW_POWER_DISABLED 0b00000000
94 #define LP_LOW_POWER_ENABLED 0b00001000
95 #define Z_AXIS_ENABLED 0b00000100
96 #define Z_AXIS_DISABLED 0b00000000
97 #define Y_AXIS_ENABLED 0b00000010
98 #define Y_AXIS_DISABLED 0b00000000
99 #define X_AXIS_ENABLED 0b00000001
100 #define X_AXIS_DISABLED 0b00000000
101 
102 #define SET_CTRL_REG1_A( ODR, LPEN, ZEN, YEN, XEN ) ODR | LPEN | ZEN | YEN | XEN
103 /*
104  * END OF POWER SETTINGS
105  */
106 
107 /*
108  * HIGH PASS FILTER SETTINGS - REGISTER : CTRL_REG2_A 0x21
109  */
110 #define HIGHPASS_MODE_NORMAL_WITH_RESET 0b00000000
111 #define HIGHPASS_MODE_REFERENCE_SIGNAL 0b01000000
112 #define HIGHPASS_MODE_NORMAL 0b10000000
113 #define HIGHPASS_MODE_AUTO_RESET_ON_INTERRUPT 0b11000000
114 /*
115  * FDS = Filtered Data Selection
116  */
117 #define HIGHPASS_FDS_INTERNAL_BYPASSED_ENABLED 0b00001000
118 #define HIGHPASS_FDS_INTERNAL_BYPASSED_DISABLED 0b00000000
119 #define HIGHPASS_FILTER_ENABLED_FOR_CLICK 0b00000100
120 #define HIGHPASS_FILTER_DISABLED_FOR_CLICK 0b00000000
121 #define HIGHPASS_FILTER_DISABLED_AOI_INT2 0b00000000
122 #define HIGHPASS_FILTER_ENABLED_AOI_INT2 0b00000010
123 #define HIGHPASS_FILTER_ENABLED_AOI_INT1 0b00000001
124 #define HIGHPASS_FILTER_DISABLED_AOI_INT1 0b00000000
125 
126 #define SET_CTRL_REG2_A( HIGHPASS_MODE, HIGHPASS_FDS, HIGHPASS_CLICK_FILTER, HIGHPASS_AOI_INT2, HIGHPASS_AOI_INT1 ) HIGHPASS_MODE | HIGHPASS_FDS | HIGHPASS_CLICK_FILTER | HIGHPASS_AOI_INT2 | HIGHPASS_AOI_INT1
127 /*
128  * END OF HIGH PASS FILTER SETTINGS
129  */
130 
131 /*
132  * INTERRUPT SETTINGS - REGISTER : CTRL_REG3_A 0x22
133  */
134 #define CLICK_INTERRUPT_ON_INT1_ENABLED 0b10000000
135 #define CLICK_INTERRUPT_ON_INT1_DISABLED 0b00000000
136 #define AOI1_INTERRUPT_ON_INT1_ENABLED 0b01000000
137 #define AOI1_INTERRUPT_ON_INT1_DISABLED 0b00000000
138 #define AOI2_INTERRUPT_ON_INT1_ENABLED 0b00100000
139 #define AOI2_INTERRUPT_ON_INT1_DISABLED 0b00000000
140 #define DRDY1_INTERRUPT_ON_INT1_ENABLED 0b00010000
141 #define DRDY1_INTERRUPT_ON_INT1_DISABLED 0b00000000
142 #define DRDY2_INTERRUPT_ON_INT1_ENABLED 0b00001000
143 #define DRDY2_INTERRUPT_ON_INT1_DISABLED 0b00000000
144 #define FIFO_WTM_INTERRUPT_ON_INT1_ENABLED 0b00000100
145 #define FIFO_WTM_INTERRUPT_ON_INT1_DISABLED 0b00000000
146 #define FIFO_OVERRUN_INTERRUPT_ON_INT1_ENABLED 0b00000010
147 #define FIFO_OVERRUN_INTERRUPT_ON_INT1_DISABLED 0b00000000
148 
149 #define SET_CTRL_REG3_A( CLICK, AOI1, AOI2, DRDY1, DRDY2, WTM, OVERRUN ) CLICK | AOI1 | AOI2 | DRDY1 | DRDY2 | WTM | OVERRUN
150 /*
151  * END OF INTERRUPT SETTINGS
152  */
153 
154 /*
155  * RESOLUTION AND SCALE SETTINGS - REGISTER : CTRL_REG4_A 0x23
156  */
157 #define BDU_UPDATE_REGISTERS_CONTINUOUSLY 0b00000000
158 #define BDU_WAIT_UNTIL_REGISTERS_ARE_READ 0b10000000
159 #define BLE_DATA_LSB_AT_LOWER_ADDRESS 0b00000000
160 #define BLE_DATA_MSB_AT_LOWER_ADDRESS 0b01000000
161 #define FS_SCALE_AT_PLUS_MINUS_2G 0b00000000
162 #define FS_SCALE_AT_PLUS_MINUS_4G 0b00010000
163 #define FS_SCALE_AT_PLUS_MINUS_8G 0b00100000
164 #define FS_SCALE_AT_PLUS_MINUS_16G 0b00110000
165 #define HR_HI_RES_ENABLED 0b00001000
166 #define HR_HI_RES_DISABLED 0b00000000
167 #define SIM_SERIAL_INTERFACE_4_WIRE 0b00000000
168 #define SIM_SERIAL_INTERFACE_3_WIRE 0b00000001
169 
170 #define SET_CTRL_REG4_A( BDU, BLE, FS, HR, SIM ) BDU | BLE | FS | HR | SIM
171 /*
172  * END OF RESOLUTION AND SCALE SETTINGS
173  */
174 
175 /*
176  * REGISTER : CTRL_REG5_A 0x24
177  */
178 #define BOOT_REBOOT_MEM_CONTENT_ENABLED 0b10000000
179 #define BOOT_REBOOT_MEM_CONTENT_DISABLED 0b00000000
180 #define FIFO_ENABLED 0b01000000
181 #define FIFO_DISABLED 0b00000000
182 #define LIR_INT1_LATCHED 0b00001000
183 #define LIR_INT1_NOT_LATCHED 0b00000000
184 #define D4D_INT1_4D_ENABLED 0b00000100
185 #define D4D_INT1_4D_DISABLED 0b00000000
186 #define LIR_INT2_LATCHED 0b00000010
187 #define LIR_INT2_NOT_LATCHED 0b00000000
188 #define D4D_INT2_4D_ENABLED 0b00000001
189 #define D4D_INT2_4D_DISABLED 0b00000000
190 
191 #define SET_CTRL_REG5_A( BOOT, FIFO_EN, LIR_INT1, D4D_INT1, LIR_INT2, D4D_INT2 ) BOOT | FIFO_EN | LIR_INT1 | D4D_INT1 | LIR_INT2 | D4D_INT2
192 /*
193  * END OF REGISTER
194  */
195 
196 /*
197  * REGISTER : CTRL_REG6_A 0x25
198  */
199 #define I2_CLICK_INTERRUPT_ON_PAD2_ENABLED 0b10000000
200 #define I2_CLICK_INTERRUPT_ON_PAD2_DISABLED 0b00000000
201 #define I2_INTERRUPT_1_ENABLED 0b01000000
202 #define I2_INTERRUPT_1_DISABLED 0b00000000
203 #define I2_INTERRUPT_2_ENABLED 0b00100000
204 #define I2_INTERRUPT_2_DISABLED 0b00000000
205 #define BOOT_I1_REBOOT_MEMORY_ENABLED 0b00010000
206 #define BOOT_I1_REBOOT_MEMORY_DISABLED 0b00000000
207 #define P2_ACT_ACTIVE_FUNCTION_ON_PAD2_ENABLED 0b00001000
208 #define P2_ACT_ACTIVE_FUNCTION_ON_PAD2_DISABLED 0b00000000
209 #define H_LACTIVE_INTERRUPT_ACTIVE_HIGH 0b00000000
210 #define H_LACTIVE_INTERRUPT_ACTIVE_LOW 0b00000010
211 
212 #define SET_CTRL6_REG_A( I2_CLICK, I2_INT1, I2_INT2, BOOT_I1, P2_ACT, H_LACTIVE ) I2_CLICK | I2_INT1 | I2_INT2 | BOOT_I1 | P2_ACT | H_LACTIVE
213 /*
214  * END OF REGISTER
215  */
216 
217 /*
218  * REGISTER : FIFO_CTRL_REG_A 0x2E
219  */
220 #define FM_BYPASS_MODE 0b00000000
221 #define FM_FIFO_MODE 0b01000000
222 #define FM_STREAM_MODE 0b10000000
223 #define FM_TRIGGER_MODE 0b11000000
224 #define TR_TRIGGER_LINKED_TO_INTERRUPT1 0b00000000
225 #define TR_TRIGGER_LINKED_TO_INTERRUPT2 0b00100000
226 
227 #define SET_FIFO_CTRL_REG_A( FM, TR ) FM | TR
228 /*
229  * END OF REGISTER
230  */
231 
232 /*
233 * REGISTER INT1_CFG_A 0x30 & INT2_CFG_A 0x31
234 */
235 #define AOI_OR_COMBINATION 0b00000000
236 #define AOI_6D_MOVEMENT_RECOGNITION_ENABLED 0b01000000
237 #define AOI_AND_COMBINATION 0b10000000
238 #define AOI_6D_POSITION_RECOGNITION_ENABLED 0b11000000
239 #define ZHIE_INTERRUPT_ON_Z_HIGH_ENABLED 0b00100000
240 #define ZHIE_INTERRUPT_ON_Z_HIGH_DISABLED 0b00000000
241 #define ZLIE_INTERRUPT_ON_Z_LOW_ENABLED 0b00010000
242 #define ZLIE_INTERRUPT_ON_Z_LOW_DISABLED 0b00000000
243 #define YHIE_INTERRUPT_ON_Y_HIGH_ENABLED 0b00001000
244 #define YHIE_INTERRUPT_ON_Y_HIGH_DISABLED 0b00000000
245 #define YLIE_INTERRUPT_ON_Y_LOW_ENABLED 0b00000100
246 #define YLIE_INTERRUPT_ON_Y_LOW_DISABLED 0b00000000
247 #define XHIE_INTERRUPT_ON_X_HIGH_ENABLED 0b00000010
248 #define XHIE_INTERRUPT_ON_X_HIGH_DISABLED 0b00000000
249 #define XLIE_INTERRUPT_ON_X_LOW_ENABLED 0b00000001
250 #define XLIE_INTERRUPT_ON_X_LOW_DISABLED 0b00000000
251 
252 #define SET_INT1_CFG_A( AOI, ZHIE, ZLIE, YHIE, YLIE, XHIE, XLIE ) AOI | ZHIE | ZLIE | YHIE | YLIE | XHIE | XLIE
253 #define SET_INT2_CFG_A( AOI, ZHIE, ZLIE, YHIE, YLIE, XHIE, XLIE ) AOI | ZHIE | ZLIE | YHIE | YLIE | XHIE | XLIE
254 /*
255  * END OF REGISTER
256  */
257 
258 /*
259  * CLICK_CFG_A 0x38
260  */
261 #define ZD_DOUBLECLICK_ON_Z_AXIS_ENABLED 0b00100000
262 #define ZD_DOUBLECLICK_ON_Z_AXIS_DISABLED 0b00000000
263 #define ZS_SINGLECLICK_ON_Z_AXIS_ENABLED 0b00010000
264 #define ZS_SINGLECLICK_ON_Z_AXIS_DISABLED 0b00000000
265 #define YD_DOUBLECLICK_ON_Y_AXIS_ENABLED 0b00001000
266 #define YD_DOUBLECLICK_ON_Y_AXIS_DISABLED 0b00000000
267 #define YS_SINGLECLICK_ON_Y_AXIS_ENABLED 0b00000100
268 #define YS_SINGLECLICK_ON_Y_AXIS_DISABLED 0b00000000
269 #define XD_DOUBLECLICK_ON_X_AXIS_ENABLED 0b00000010
270 #define XD_DOUBLECLICK_ON_X_AXIS_DISABLED 0b00000000
271 #define XS_SINGLECLICK_ON_X_AXIS_ENABLED 0b00000001
272 #define XS_SINGLECLICK_ON_X_AXIS_DISABLED 0b00000000
273 
274 #define SET_CLICK_CFG_A( ZD, ZS, YD, YS, XD, XS ) ZD | ZS | YD | YS | XD | XS
275 /*
276  * END OF CLICK_CFG_A
277  */
278 
279 /*
280  * CLICK_SRC_A 0x39
281  */
282 #define IA_INTERRUPT_ACTIVE_NO_INTERRUPTS 0b00000000
283 #define IA_INTERRUPT_ACTIVE_1_OR_MORE_INTERRUPTS 0b01000000
284 #define DCLICK_DOUBLE_CLICK_DETECTION_ENABLED 0b00000000
285 #define DCLICK_DOUBLE_CLICK_DETECTION_DISABLED 0b00100000
286 #define SCLICK_SINGLE_CLICK_DETECTION_ENABLED 0b00000000
287 #define SCLICK_SINGLE_CLICK_DETECTION_DISABLED 0b00010000
288 #define SIGN_POSITIVE_DETECTION 0b00000000
289 #define SIGN_NEGATIVE_DETECTION 0b00001000
290 
291 #define SET_CLICK_SRC_A( DCLICK, SCLICK, SIGN ) DCLICK | SCLICK | SIGN
292 /*
293  * END OF CLICK_SRC_A
294  */
295 
296 /*
297  * CRA_REG_M 0x00
298  */
299 #define TEMP_ENABLED 0b10000000
300 #define TEMP_DISABLED 0b00000000
301 #define DO2_0_75Hz 0b00000000
302 #define DO2_1_5Hz 0b00000100
303 #define DO2_3_0Hz 0b00001000
304 #define DO2_7_5Hz 0b00001100
305 #define DO2_15Hz 0b00010000
306 #define DO2_30Hz 0b00010100
307 #define DO2_75Hz 0b00011000
308 #define DO2_220Hz 0b00011100
309 
310 #define SET_CRA_REG_M( TEMP_EN, DO2 ) TEMP_EN | DO2
311 /*
312  * END OF CRA_REG_M
313  */
314 
315 /*
316  * CRB_REG_M 0x01
317  */
318 #define GAIN_RANGE_1_3_GAIN_X_Y_Z_1100_GAIN_Z_980 0b00100000
319 #define GAIN_RANGE_1_9_GAIN_X_Y_Z_855_GAIN_Z_760 0b01000000
320 #define GAIN_RANGE_2_5_GAIN_X_Y_Z_670_GAIN_Z_600 0b01100000
321 #define GAIN_RANGE_4_0_GAIN_X_Y_Z_450_GAIN_Z_400 0b10000000
322 #define GAIN_RANGE_4_7_GAIN_X_Y_Z_400_GAIN_Z_355 0b10100000
323 #define GAIN_RANGE_5_6_GAIN_X_Y_Z_330_GAIN_Z_295 0b11000000
324 #define GAIN_RANGE_8_1_GAIN_X_Y_Z_230_GAIN_Z_205 0b11100000
325 
326 #define SET_CRB_REG_M( GAIN ) GAIN
327 /*
328  * END OF CRB_REG_M
329  */
330 
331 /*
332  * MR_REG_M 0x02
333  */
334 #define MD_CONTINUOUS_CONVERSION_MODE 0b00000000
335 #define MD_SINGLE_CONVERSION_MODE 0b00000001
336 #define MD_SLEEP_MODE_1 0b00000010
337 #define MD_SLEEP_MODE_2 0b00000011
338 
339 #define SET_MR_REG_M( MD ) MD
340 /*
341  * END OF MR_REG_M
342  */
343 
344 namespace quadro {
345 
346  namespace i2c {
347 
351  class LSM303DLHC : public i2cDevice {
352 
353  public:
354 
358  LSM303DLHC();
359 
363  ~LSM303DLHC();
364 
369 
376  uint8_t getPowerSettings() { return powerSettings; }
377 
384  uint8_t getHighPassSettings() { return highPassSettings; }
385 
392  uint8_t getInt1Settings() { return int1Settings; }
393 
400  uint8_t getDataSettings() { return dataSettings; }
401 
408  uint8_t getMemorySettings() { return memorySettings; }
409 
416  uint8_t getInterruptSettings() { return interruptSettings; }
417 
424  uint8_t getFIFOSettings() { return FIFOSettings; }
425 
432  uint8_t getInterrupt1CFGSettings() { return interrupt1CFGSettings; }
433 
440  uint8_t getInterrupt2CFGSettings() { return interrupt2CFGSettings; }
441 
448  uint8_t getClickCFGSettings() { return clickCFGSettings; }
449 
456  uint8_t getClickSRCSettings() { return clickSRCSettings; }
457 
464  uint8_t getCRARegMSettings() { return CRARegMSettings; }
465 
472  uint8_t getMRRegMSettings() { return MRRegMSettings; }
473 
480  void startSensorThread();
481 
482  short x;
483  short y;
484  short z;
485 
486  unsigned int dataTimer;
487 
488  protected:
489 
495  void setDeviceAddress( unsigned char _deviceAddress ) { deviceAddress = _deviceAddress; }
496 
502  void setBusId( int _busId ) { busId = _busId; }
503 
504  private:
505 
513  uint8_t commitSetting( uint8_t registerAddress, uint8_t registerValue );
514 
515  uint8_t powerSettings;
516 
517  uint8_t highPassSettings;
518  uint8_t int1Settings;
519  uint8_t dataSettings;
520  uint8_t memorySettings;
521  uint8_t interruptSettings;
522  uint8_t FIFOSettings;
523  uint8_t interrupt1CFGSettings;
524  uint8_t interrupt2CFGSettings;
525  uint8_t clickCFGSettings;
526  uint8_t clickSRCSettings;
527  uint8_t CRARegMSettings;
528  uint8_t MRRegMSettings;
529 
535  static void* recordAccelerometerValues( void* _LSM303 );
536 
543  static void* recordMagnetometerValues( void* _LSM303 );
544 
548  void setAccelerometerTimerBasedOnODR();
549 
553  void setMagnetometerTimerBasedOnDO();
554 
558  void startRecording();
559 
563  void stopRecording();
564 
568  void setDataTimer();
569 
576  short getX();
577 
584  short getY();
585 
592  short getZ();
593 
597  void setX();
598 
602  void setY();
603 
607  void setZ();
608 
614  uint8_t magnetometerIsEnabled();
615 
621  uint8_t getOutputDataRate();
622 
623 
629  uint8_t getDataOutputRate();
630 
636  bool XAxisIsEnabled();
637 
643  bool YAxisIsEnabled();
644 
650  bool ZAxisIsEnabled();
651 
652  pthread_t LSM303AccelThread, LSM303MagThread;
653 
654  int threadRet;
655 
656  };
657 
658  }
659 }
660 #endif /* SRC_LSM303DLHC_H_ */
unsigned char registerAddress
Definition: i2cDevice.h:225
LSM303DLHC()
Definition: LSM303DLHC.cpp:182
uint8_t getInt1Settings()
Definition: LSM303DLHC.h:392
uint8_t getInterrupt2CFGSettings()
Definition: LSM303DLHC.h:440
uint8_t getMRRegMSettings()
Definition: LSM303DLHC.h:472
uint8_t getDataSettings()
Definition: LSM303DLHC.h:400
uint8_t getHighPassSettings()
Definition: LSM303DLHC.h:384
uint8_t getClickSRCSettings()
Definition: LSM303DLHC.h:456
unsigned int dataTimer
set from the devices data rate settings
Definition: LSM303DLHC.h:484
Definition: i2cDevice.h:34
void setDeviceAddress(unsigned char _deviceAddress)
Definition: LSM303DLHC.h:495
uint8_t getInterruptSettings()
Definition: LSM303DLHC.h:416
void loadRecommendedFlightSettings()
Definition: LSM303DLHC.cpp:22
Definition: LSM303DLHC.h:351
~LSM303DLHC()
Definition: LSM303DLHC.cpp:187
int busId
Definition: i2cDevice.h:232
unsigned char deviceAddress
Definition: i2cDevice.h:223
Definition: aeronautics.h:23
uint8_t getClickCFGSettings()
Definition: LSM303DLHC.h:448
uint8_t getMemorySettings()
Definition: LSM303DLHC.h:408
uint8_t getInterrupt1CFGSettings()
Definition: LSM303DLHC.h:432
uint8_t getFIFOSettings()
Definition: LSM303DLHC.h:424
unsigned char registerValue
Definition: i2cDevice.h:224
void setBusId(int _busId)
Definition: LSM303DLHC.h:502
uint8_t getPowerSettings()
Definition: LSM303DLHC.h:376
uint8_t getCRARegMSettings()
Definition: LSM303DLHC.h:464
void startSensorThread()
Definition: LSM303DLHC.cpp:192